Many obstacles exist to further miniaturization of semiconductor components. Among these obstacles include the filling of metal interconnect layers to insure proper operation of the devices. Metal interconnect signal lines establish contact with lower conductive layers of the integrated circuit through vias that are formed in an insulating layer. It is desirable to completely fill the via with the metal that is used to form the interconnect layer so as to ensure optimal operation of the device.
For reasons of its cost, physical properties and availability, aluminum is presently the metal of choice for the fabrication of metal interconnect lines in integrated circuits. The interconnect lines are typically formed by a sputtering process, which can result in less than optimal filling of the contact vias. For example, problems can arise from the accumulation of relatively large amounts of aluminum at the upper surface of the insulating layer. The accumulation of Aluminum at the edges of the contact via can block or otherwise obstruct the via prior to the delivery of aluminum in sufficient quantity to completely fill the via, resulting in the formation of voids and uneven structures within the via. This problem is particularly acute as integrated circuits are fabricated using smaller geometries. The finer dimensioned contacts that are used in smaller geometry devices, such as the current 0.5 .mu.m and future generations of scaled technologies, necessarily have a larger aspect ratio (i.e., relationship of height to width) than do larger geometry devices, thereby exacerbating the via filling difficulties described above. For example, unduly large voids can result in contact resistance that is appreciably higher than designed. In addition, thinner regions of the aluminum layer adjacent to the via fill region will be subject to electromigration, which can result in the eventual opening of the circuits and failure of the device.
A number of different approaches have been attempted to ensure optimal metal contact at lower interconnect levels. For example, refractory metal layers have been used in conjunction with an aluminum interconnect layer to improve conduction throughout a via. In addition, via side walls have been sloped so as to improve metal step delivery into vias. The use of sloped side walls, however, has become less desirable as the industry adopts smaller device geometries. Even with the geometries above 0.5 .mu.m, the foregoing techniques have not completely overcome the difficulties in the via filling. It is believed that the problem of via filling in the past has been at least partially attributable to the relatively low pressures and low temperatures at which the aluminum was processed incident to via filling. These temperatures typically are below 500.degree. C., which some manufacturers believe contributes to the formation of aluminum grain sizes that are unduly large for via filling.
U.S. Pat. No. 5,108,951 to Chen, et al., which issued on Apr. 28, 1992, attempts to address the foregoing problem of via filling arising from the flow of aluminum grains of unduly large size. In the Chen patent, the temperature of the integrated circuit is heated to a temperature of about 400.degree. C. prior to the commencement of aluminum deposition. Aluminum is deposited into the via at a rate of about 30-80 .ANG./sec during the course of wafer heating to a temperature of about 500.degree. C. This prior art system shares many of the same disadvantages of the previously addressed prior art, namely incomplete via filling, particularly at smaller via geometries. In addition, via filling is undertaken at temperatures in the vicinity of about 500.degree. C., which effectively prohibits the use as dielectrics of many of the new generation of low dielectric constant polymeric materials, as these polymeric materials typically decompose at such high temperatures.
In view of the foregoing deficiencies in the prior art, it is desirable to provide an integrated circuit filling process for contacts and vias which provides for a reliable filling at relatively low temperatures, preferably on the order of about 250.degree.-400.degree. C. or cooler. Contact and via filling at such low temperatures will permit for the use of lower dielectric constant dielectric materials such as parylene, aerogels and xerogels in semiconductor fabrication. The use of such low dielectric constant dielectrics is believed to constitute a significant aspect of the development of forthcoming generations of sub-0.5 .mu.m technologies.